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STR71xF
ARM7TDMITM 16/32-BIT MCU WITH FLASH, USB, CAN 5 TIMERS, ADC, 10 COMMUNICATIONS INTERFACES
PRODUCT PREVIEW

Memories - Up to 272 Kbytes (256+16K) FLASH program memory (100,000 cycles endurance, data retention 20 years) - Up to 64 Kbytes RAM - External Memory Interface (EMI) for up to 4 banks of SRAM, Flash, ROM. - Multi-boot capability Clock, Reset and Supply Management - 3.3V application supply and I/O interface - Embedded 1.8V voltage regulator for core supply - 0 to 16 MHz external main oscillator - 32 kHz external backup oscillator - Internal PLL for CPU clock - Up to 50 MHz CPU operating frequency when executing from flash - Realtime Clock for clock-calendar function - 4 power saving modes: SLOW, WAIT, STOP and STANDBY modes Nested interrupt controller - Fast interrupt handling with multiple vectors - 32 vectors with 16 IRQ priority levels - 2 maskable FIQ sources Up to 48 I/O ports - 30/32/48 multifunctional bidirectional I/O lines - 14 ports with interrupt capability 5 Timers - 16-bit watchdog timer - Four 16-bit timers each with: 2 input captures, 2 output compares, PWM and pulse counter modes
TQFP64 10 x 10
TQFP144 20 x 20
10 Communications Interfaces - 2 I2C interfaces (1 multiplexed with SPI) - 4 UART asynchronous serial communications interfaces - Smart Card ISO7816-3 interface on UART1 - 2 BSPI synchronous serial interfaces - CAN interface (2.0B Active) - USB v 2.0 Full Speed (12Mbit/s) Device Function with Suspend and Resume support - HDLC synchronous communications interface 4-channel 12-bit A/D Converter - Conversion time: - 4 channels: up to 500 Hz (2 ms) - 1 channel: up to 1 kHz (1 ms) - Conversion range: 0 to 2.5V Development Tools Support - JTAG with debug mode trigger request
Table 1. Device Summary
Features FLASH memory - Kbytes RAM - Kbytes Peripheral Functions Operating Voltage Operating Temperature Packages TQFP144 20x20 STR710F Z1T6 Z2T6 128+16 256+16 16 64 CAN, EMI, USB, 48 I/Os STR711F R1T6 R2T6 128+16 256+16 16 USB, 30 I/Os 3.0 to 3.6V (optional 1.8V for core) -40 to +85C TQFP64 10x10 64 STR712F R1T6 R2T6 128+16 256+16 16 CAN, 32 I/Os 64
Rev. 4
October 2004 1/39
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3 LVD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.5 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.6 nRSTIN Input Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.7 Oscillator Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.8 PLL Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.9 Flash Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.10 External Memory Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.11 ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.1 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4 ORDER CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Note: For detailed information on the STR71xF Microcontroller memory, registers and peripherals. please refer to the STR71xF Reference Manual.
39
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1
STR71xF
1 INTRODUCTION
This Product Preview provides the STR71x Ordering Information, Mechanical and Electrical Device Characteristics. For complete information on the STR71xF Microcontroller memory, registers and peripherals. please refer to the STR71xF Reference Manual. For information on the ARM7TDMI core please refer to the ARM7TDMI Technical Reference Manual. 1.1 Overview ARM(R) core with embedded Flash & RAM The STR71xF series is a family of ARM-powered 16/32bit Micro-controllers with embedded Flash and RAM. It combines the high performance ARM7TDMI CPU with an extensive range of peripheral functions and enhanced I/O capabilities. All devices have on-chip high-speed single voltage FLASH memory and high-speed RAM. The STR71xF family has an embedded ARM core and is therefore compatible with all ARM tools and software. For information on the ARM Realview Developer Kit for ST and third-party development tools, please refer to the http://www.st.com website Package Choice: Low Pin-Count TQFP64 or Feature-Rich TQFP144 The STR71xF family is available in 2 package sizes. The 144-pin version has the full set of all features including CAN, USB and External Memory Interface. The two 64-pin versions do not include External Memory Interface and give you the choice of either CAN or USB. Optional External Memory (STR710F) The non-multiplexed 16-bit data/24-bit address bus available on the STR710F (TQFP144) supports four 16-Mbyte banks of external memory. Wait states are programmable individually for each bank allowing different memory types (Flash, EPROM, ROM, SRAM etc.) to be used to store programs or data. Figure 1 shows the general block diagram of the device family. Flexible Power Management
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1
STR71xF
To minimize power consumption, you can program the STR71xF to switch to SLOW, WAIT FOR INTERRUPT, STOP or STANDBY mode depending on the current system activity in the application. Flexible Clock Control Two external clock sources can be used, a main clock and a 32 kHz backup clock. The embedded PLL allows the internal system clock (up to 50 MHz) to be generated from a main clock frequency of 16 MHz or less. The PLL output frequency can be programmed using a wide selection of multipliers and dividers. Voltage Regulators The STR71xF requires an external 3.0-3.6V power supply. There are two internal Voltage Regulators for generating the 1.8V power supply for the core and peripherals. The main VR is switched off and the Low Power VR switched on when the application puts the STR71xF in Standby or Low Power Wait for Interrupt (LPWFI) mode. Low Voltage Detectors Each voltage regulator has an embedded LVD that monitors the internal 1.8V supply. If the voltage drops below a certain threshold, the LVD will reset the STR71xF. On-Chip Peripherals CAN Interface (STR710F and STR712F) The CAN module is compliant with the CAN specification V2.0 part B (active). The bit rate can be programmed up to 1 MBaud. USB Interface (STR710F and STR711F) The full-speed USB interface is USB V2.0 compliant and provides up to 8 bidirectional/16 unidirectional endpoints, up to 12 Mb/s (full-speed), support for bulk transfer and USB Suspend/Resume functions. Standard Timers Each of the four timers have a 16-bit free-running counter with 7-bit prescaler, up to two input capture/output compare functions, a pulse counter function, and a PWM channel with selectable frequency. Realtime Clock (RTC) The RTC provides a set of continuously running counters driven by a low power 32kHz internal oscillator. The RTC can be used as a general timebase or clock/calendar/alarm function. When the STR71xF is in Standby mode the RTC can be kept running, powered by the low power voltage regulator and driven by the 32kHz internal oscillator. UARTs
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1
STR71xF
The 4 UARTs allow full duplex, asynchronous, communications with external devices with independently programmable TX and RX baud rates up to 625 kb/s. Smart Card Interface UART1 is configurable to function either as a general purpose UART or as an asynchronous Smart Card interface as defined by ISO 7816-3. It includes Smart Card clock generation and provides support features for synchronous cards. Buffered Serial Peripheral Interfaces (BSPI) Each of the two SPIs allow full duplex, synchronous communications with external devices, master or slave communication at up to 5.5Mb/s in Master mode and 4 Mb/s in Slave mode. I2C Interfaces The two I2C Interfaces provide multi-master and slave functions, support normal and fast I2C mode (400 kHz) and 7 or 10-bit addressing modes. One I2C Interface is multiplexed with one SPI, so either 2xSPI+1x I2C or 1xSPI+2x I2C may be used at a time. HDLC interface The High Level Data Link Controller (HDLC) unit supports full duplex operation and NRZ, NRZI, FM0 or MANCHESTER protocols. It has an internal 8-bit baud rate generator. A/D Converter The Analog to Digital Converter, converts in single channel or up to 4 channels in single-shot or continuous conversion modes. Resolution is 12-bit with a sample rate of 0.5 kHz (1 kHz in single channel mode). The input voltage range is 0-2.5V. Watchdog The 16-bit Watchdog Timer protects the application against hardware or software failures and ensures recovery by generating a reset. I/O Ports The 48 I/O ports are programmable as Inputs or Outputs. External Interrupts Up to 14 external interrupts are available for application use or to wake-up the application from STOP mode.
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STR71xF
Figure 1. STR71xF Block Diagram
A[19:0] D[15:0] RDN WEN[1:0]
A[23:20] CS[3:0)
CK CKOUT RSTIN
PRCCU/PLL
EXT. MEM. INTERFACE (EMI) FLASH MEMORY 144/272K
ARM7DMI CPU JTDI JTCK JTMS JTRST JTDO DBGRQS BOOTEN
ARM7 NATIVE BUS
JTAG
RAM 16/64K APB BRIDGE 1
V18[1:0] V33[6:0] VSS[9:0] V18BKP AVDD AVSS
POWER SUPPLY VREG
APB BRIDGE 2 I2C0 2 AF 2 AF 4 AF 4 AF 2 AF 3 AF 2 AF 2 AF 3 AF USBDP USBDN 1 AF
INTERRUPT CTL(EIC) 4 AF A/D TIMER0 4 AF 2 AF 4 AF OSC 14 AF TIMER1
APB BUS
I2C1 BSPI0 BSPI1 UART0 UART1 / SMART CARD UART2 UART3 HDLC
TIMER2 TIMER3 RTC
APB BUS
STDBY RTCXTO RTCXTI WAKEUP
EXT INT (XTI) WATCHDOG
USB P0[15:0] P1[15:0] P2[15:0] I/O PORT 0 I/O PORT 1 CAN I/O PORT 2
2 AF
AF: alternate function on I/O port pin
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1.2 Related Documentation Available from www.arm.com: ARM7TDMI Technical Reference Manual Available from http://www.st.com: STR71x Reference Manual AN1774 - Getting Started with STR71xF Software development AN1775 - Getting Started with STR71xF Hardware development AN1776 - STR71xF Enhanced Interrupt Controller AN1777 - STR71xF Memory Mapping AN1778 - STR71xF Multi-ICE Setup AN1780 - Real Time Clock with STR71xF AN1781 - Four 7 Segment Display Drive Using the STR71xF The above is a selected list only, a full list STR71x application notes can be viewed at http://www.st.com.
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1.3 Pin Description
Figure 2. STR710F Package Pinout
P0.9/U0.TX/BOOT.0 P0.8/U0.RX/U0.TX P0.7/S1.SSN P0.6/S1.SCLK P0.5/S1.MOSI VSS V33 WEn.0 WEn.1 A.19 A.18 A.17 A.16 A.15 A.14 V18 VSS18 P0.4/S1.MISO P0.3/S0.SSN/I1.SDA P0.2/S0.SCLK/I1.SCL P0.1/S0.MOSI/U3.RX P0.0/S0.MISO/U3.TX A.13 A.12 A.11 A.10 A.9 A.8 A.7 A.6 A.5 V33 VSS P1.15/HTXD N.C. N.C. P0.10/U1.RX/U1.TX/SCDATA RDn P0.11/U1.TX/BOOT.1 P0.12/SCCLK VSS V33 P2.0/CSn.0 P2.1/CSn.1 P0.13/U2.RX/T2.OCMPA P0.14/U2.TX/T2.ICAPA P2.2/CSn.2 P2.3/CSn.3 P2.4/A.20 P2.5/A.21 P2.6/A.22 BOOTEN P2.7/A.23 P2.8 N.C. N.C. VSS V33 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 JTDI JTMS JTCK JTDO JTRSTn NU TEST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
TQFP144
P1.14/HRXD/I0.SDA P1.13/HCLK/I0.SCL P1.10/USBCLK P1.9 V33 VSS A.4 A.3 A.2 A.1 A.0 D.15 D.14 D.13 D.12 D.11 D.10 USBDN USBDP P1.12/CANTX P1.11/CANRX N.C. P1.8 P1.7/T1.OCMPA VSSIO-PLL V33IO-PLL D.9 D.8 D.7 D.6 D.5 P1.6/T1.OCMPB P1.5/T1.ICAPB P1.4/T1.ICAPA P1.3/T3.ICAPB/AIN.3 P1.2/T3.OCMPA/AIN.2
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N.C. TEST N.C. V33IO-PLL N.C. VSSIO-PLL N.C. DBGRQS CKOUT CK P0.15/WAKEUP N.C. RTCXTI RTCXTO STDBYn RSTINn N.C. VSSBKP V18BKP N.C. N.C. V18 VSS18 N.C. D.0 D.1 D.2 D.3 D.4 AVDD AVSS N.C. N.C. N.C. P1.0/T3.OCMPB/AIN.0 P1.1/T3.ICAPA/AIN.1
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
STR71xF
Figure 3. STR712F Package Pinout
P0.9/U0.TX/BOOT.0 P0.8/U0.RX/U0.TX P0.7/S1.SSN P0.6/S1.SCLK P0.5/S1.MOSI VSS V18 VSS18 P0.4/S1.MISO P0.3/S0.SSN/I1.SDA P0.2/S0.SCLK/I1.SCL P0.1/S0.MOSI/U3.RX P0.0/S0.MISO/U3.TX V33 VSS P1.15/HTXD P0.10/U1.RX/U1.TX/SCDATA P0.11/U1.TX/BOOT.1 P0.12/SCCLK VSS P0.13/U2.RX/T2.OCMPA P0.14/U2.TX/T2.ICAPA BOOTEN VSS V33 JTDI JTMS JTCK JTDO nJTRST NU TEST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
TQFP64
P1.14/HRXD/I0.SDA P1.13/HCLK/I0.SCL P1.10 P1.9 VSS P1.12/CANTX P1.11/CANRX P1.8 P1.7/T1.OCMPA VSSIO-PLL V33IO-PLL P1.6/T1.OCMPB P1.5/T1.ICAPB P1.4/T1.ICAPA P1.3/T3.ICAPB/AIN.3 P1.2/T3.OCMPA/AIN.2
V33IO-PLL VSSIO-PLL CK P0.15/WAKEUP RTCXTI RTCXTO nSTDBY nRSTIN VSSBKP V18BKP V18 VSS18 AVDD AVSS P1.0/T3.OCMPB/AIN.0 P1.1/T3.ICAPA/AIN.1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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Figure 4. STR711F Package Pinout
P0.9/U0.TX/BOOT.0 P0.8/U0.RX/U0.TX P0.7/S1.SSN P0.6/S1.SCLK P0.5/S1.MOSI VSS V18 VSS18 P0.4/S1.MISO P0.3/S0.SSN/I1.SDA P0.2/S0.SCLK/I1.SCL P0.1/S0.MOSI/U3.RX P0.0/S0.MISO/U3.TX V33 VSS P1.15/HTXD P0.10/U1.RX/U1.TX/SCDATA P0.11/U1.TX/BOOT.1 P0.12/SCCLK VSS P0.13/U2.RX/T2.OCMPA P0.14/U2.TX/T2.ICAPA BOOTEN VSS V33 JTDI JTMS JTCK JTDO nJTRST NU TEST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
TQFP64
P1.14/HRXD/I0.SDA P1.13/HCLK/I0.SCL P1.10/USBCLK P1.9 VSS USBDN USBDP P1.8 P1.7/T1.OCMPA VSSIO-PLL V33IO-PLL P1.6/T1.OCMPB P1.5/T1.ICAPB P1.4/T1.ICAPA P1.3/T3.ICAPB/AIN.3 P1.2/T3.OCMPA/AIN.2
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V33IO-PLL VSSIO-PLL CK P0.15/WAKEUP RTCXTI RTCXTO nSTDBY nRSTIN VSSBKP V18BKP V18 VSS18 AVDD AVSS P1.0/T3.OCMPB/AIN.0 P1.1/T3.ICAPA/AIN.1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
STR71xF
Legend / Abbreviations for Table 2: Type: I = input, O = output, S = supply, HiZ= high impedance, In/Output level: C = CMOS 0.3VDD/0.7VDD CT= CMOS 0.8V / 2V with input trigger TT= TTL 0.3VDD/0.7VDD with input trigger C/T = Programmable levels: CMOS 0.3VDD/0.7VDD or TTL 0.8V / 2V Port and control configuration: - Input: pu/pd= software enabled internal pull-up or pull down pu= in reset state, the internal 100k weak pull-up is enabled. pd = in reset state, the internal 100k weak pull-down is enabled. - Output: OD = open drain (logic level) PP = push-pull T = true OD, (P-Buffer and protection diode to VDD not implemented), 5V tolerant. Note: The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to Table 3, "Port Bit Configuration Table," on page 18. The Port bit configuration at reset is PC0=1, PC1=1, PC2=0. The port data register bit (PD) value depends on the pu/pd column in Table 2 below, which specifies whether the pull-up or pull-down is enabled at reset Table 2. Device Pin Description
Pin n InputLevel TQFP144 Type TQFP64 Pin Name Input interrupt pu/ pd Output Capability Actiive in Stdby Main function (after reset)
OD
PP
Alternate function
UART1: Receive Data input 1 1 P0.10/U1.RX/ U1.TX/ SC.DATA I/O CT pd
2)
UART1: Transmit data output.
X 4mA T
Port 0.10
Note: This pin may be used for Smartcard DataIn/DataOut or single wire UART (half duplex) if programmed as Alternate Function Output. The pin will be tri-stated except when UART transmission is in progress
2
-
RD P0.11/ BOOT.1/ U1.TX
O pd
2)
X
External Memory Interface: Active low read signal for external memory. It maps to the OE_N input of the external components. Port 0.11 Port 0.12 Select Boot Con- UART1: Transmit data figuration input output. Smartcard reference clock output
3 4 5 6
2 3 4 -
I/O CT
4mA X 4mA
X
P0.12/SC.CLK I/O CT VSS V33 P2.0/CS.0 S S
pd
2)
Ground voltage for digital I/Os Supply voltage for digital I/Os External Memory Interface: Select Memory Bank 0 output Note: This pin is forced to output mode at reset to allow boot from external memory External Memory Interface: Select Memory Bank 1 output UART2: Receive Data input Timer2: Output Compare A output
7
-
I/O CT pu pu
1)
8mA X
X
Port 2.0
8 9
5
P2.1/CS.1 P0.13/U2.RX/ T2.OCMPA
I/O CT
8mA X
X X
Port 2.1 Port 0.13
I/O CT pu X 4mA X
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Pin n InputLevel TQFP144 Type TQFP64 Pin Name
Input interrupt pu/ pd
Output Capability
Actiive in Stdby
Main function (after reset) Port 0.14 Port 2.2 Port 2.3 Port 2.4
OD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
6 7 8 9 10 11 12 13 14 15 16 -
P0.14/U2.TX/ T2.ICAPA P2.2/CS.2 P2.3/CS.3 P2.4/A.20 P2.5/A.21 P2.6/A.22 BOOTEN P2.7/A.23 P2.8 N.C. N.C. VSS V33 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 JTDI JTMS JTCK JTDO JTRST NU TEST N.C.
PP
Alternate function
I/O CT pu I/O CT I/O CT I/O CT I/O CT I/O CT I CT pd
2)
4mA X 8mA X 8mA X 8mA X 8mA X 8mA X
X X X X X X
UART2: Transmit Timer2: Input Capture A data output input External Memory Interface: Select Memory Bank 3 output External Memory Interface: Select Memory Bank 4 output
pu
1)
pu
1)
pd
2)
pd
2)
Port 2.5 External Memory Interface: address bus Port 2.6 Boot control input. Enables sampling of BOOT[1:0] pins
pd
2)
I/O CT
8mA X
X X
Port 2.7 External Memory Interface: address bus Port 2.8 External interrupt INT2 Not connected (not bonded) Not connected (not bonded)
I/O CT pu X 4mA X
S S I/O CT pu X 4mA X I/O CT pu X 4mA X I/O CT pu X 4mA X I/O CT pu I/O CT pu I/O CT pu I/O CT pu I I I O I TT TT TT C 8mA X 4mA X 4mA X 4mA X 4mA X X X X X X X X
Ground voltage for digital I/Os Supply voltage for digital I/Os Port 2.9 External interrupt INT3 Port 2.10 Port 2.11 Port 2.12 Port 2.13 Port 2.14 Port 2.15 JTAG Data input. External pull-up required. JTAG Mode Selection Input. External pull-up required. JTAG Clock Input. External pull-up or pull-down required. JTAG Data output. Note: Reset state = HiZ. JTAG Reset Input. External pull-up required. Reserved, must be forced to ground. Reserved, must be forced to ground. Not connected (not bonded) External interrupt INT4
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Pin n InputLevel TQFP144 Type TQFP64 Pin Name
Input interrupt pu/ pd
Output Capability
Actiive in Stdby
Main function (after reset)
OD
38 39 40 41 42 43 44 45 46 47 48 49 50
17 18 19 20 21 22
TEST N.C. V33IO-PLL N.C. VSSIO-PLL N.C. DBGRQS CKOUT CK P0.15/WAKEUP N.C. RTCXTI RTCXTO I O I I C TT pu X 4mA X CT 8mA X S S
PP
Alternate function
Reserved, must be forced to ground. Not connected (not bonded) Supply voltage for digital I/O circuitry and for PLL reference Not connected (not bonded) Ground voltage for digital I/O circuitry and for PLL reference Not connected (not bonded) Debug Mode request input (active high) Clock output (fPCLK2) Note: Enabled by CKDIS register in APB Bridge 2 Reference clock input Port 0.15 Wakeup from Standby mode input.
Not connected (not bonded) Realtime Clock input and input of 32 kHz oscillator amplifier circuit Output of 32 kHz oscillator amplifier circuit Input: Hardware Standby mode entry input active low. Caution: External pull-up to V33 required to select normal mode.
51
23
STDBY
I/O CT
4mA X
X Output: Standby mode active low output following Software Standby mode entry. Note: In Standby mode all pins are in high impedance except those marked Active in Stdby
52 53 54
24 25
RSTIN N.C. VSSBKP
I
CT S
X Reset input Not connected (not bonded) X Stabilisation for low power voltage regulator. Stabilisation for low power voltage regulator. Requires external capacitors of at least 1F between V18BKP and X VSS18BKP. See Figure 5. Note: If the low power voltage regulator is bypassed, this pin can be connected to an external 1.8V supply. Not connected (not bonded) Not connected (not bonded) Stabilisation for main voltage regulator. Requires external capacitors of at least 10F + 33nF between V18 and VSS18. See Figure 5. Stabilisation for main voltage regulator. Not connected (not bonded)
55
26
V18BKP
S
56 57 58 59 60
27 28 -
N.C. N.C. V18 VSS18 N.C. S S
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Pin n InputLevel TQFP144 Type TQFP64 Pin Name
Input interrupt pu/ pd
Output Capability
Actiive in Stdby
Main function (after reset)
OD
61 62 63 64 65 66 67 68 69 70 71 72 73 74
29 30 31 32 33 34
D.0 D.1 D.2 D.3 D.4 VDDA VSSA N.C. N.C. N.C. P1.0/T3.OCMPB/AIN.0 P1.1/T3.ICAPA/T3.EXTCLK/AIN.1
I/O I/O I/O I/O I/O S S
8mA 8mA 8mA 8mA 8mA Supply voltage for A/D Converter Ground voltage for A/D Converter Not connected (not bonded) Not connected (not bonded) Not connected (not bonded) Timer 3: Output Compare B External Memory Interface: data bus
I/O CT pu I/O CT pu
4mA X 4mA X 4mA X 4mA X
PP
Alternate function
X X X X
Port 1.0
ADC: Analog input 0
Timer 3: Input Port 1.1 Capture A or Ex- ADC: Analog input 1 ternal Clock input Port 1.2 Port 1.3 Timer 3: Output Compare A Timer 3: Input Capture B Timer 1: Input Capture A Timer 1: Input Capture B Timer 1: Output Compare B ADC: Analog input 2 ADC: Analog input 3 Timer 1: External Clock input
P1.2/T3.OCMI/O CT pu PA/AIN.2 P1.3/ T3.ICAPB/ AIN.3 P1.4/T1.ICAPA/T1.EXTCLK P1.5/ T1.ICAPB P1.6/T1.OCMPB D.5 D.6 D.7 D.8 D.9 V33IO-PLL VSSIO-PLL I/O CT pu
75 76 77 78 79 80 81 82 83 84 85 86 87 88
35 36 37 38 39 40 41 42
I/O CT pu I/O CT pu I/O CT pu I/O I/O I/O I/O I/O S S
4mA X 4mA X 4mA X 8mA 8mA 8mA 8mA 8mA
X X X
Port 1.4 Port 1.5 Port 1.6
External Memory Interface: data bus
Supply voltage for digital I/O circuitry and for PLL reference Ground voltage for digital I/O circuitry and for PLL reference 4mA X 4mA X X X Port 1.7 Port 1.8 Not connected (not bonded) Port 1.11 CAN: receive data input Note: On STR710 and STR712 only Timer 1: Output Compare A
P1.7/T1.OCMI/O CT pu PA P1.8 N.C. P1.11/CANRX I/O CT pd
I/O CT pu X 4mA X
X
14/39
STR71xF
Pin n InputLevel TQFP144 Type TQFP64 Pin Name
Input interrupt pu/ pd
Output Capability
Actiive in Stdby
Main function (after reset) Port 1.12
OD
PP
Alternate function
89
43
P1.12/CANTX
I/O CT pu X 4mA X
X
CAN: Transmit data output Note: On STR710 and STR712 only
USB bidirectional data (data +). Reset state = HiZ 90 42 USBDP I/O CT Note: On STR710 and STR711 only This pin requires an external pull-up to V33 to maintain a high level. USB bidirectional data (data -). Reset state = HiZ Note: On STR710 and STR711 only. 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA Ground voltage for digital I/O circuitry Supply voltage for digital I/O circuitry 4mA X 4mA X X X X X Port 1.9 Port 1.10 Port 1.13 Port 1.14 USB: 48 MHZ clock input HDLC: reference clock input HDLC: Receive data input I2C clock I2C serial data External Memory Interface: address bus External Memory Interface: data bus
91 92 93 94 95 96 97 98 99 100 101 102 104
43 -
USBDN D.10 D.11 D.12 D.13 D.14 D.15 A.0 A.1 A.2 A.3 A.4 VSS V33 P1.9 P1.10/USBCLK P1.13/HCLK/ I0.SCL P1.14/HRXD/ I0.SDA N.C. N.C. P1.15/HTXD VSS V33
I/O CT I/O I/O I/O I/O I/O I/O O O O O O S S I/O CT pd I/O C/T pu
103 44 105 45 106 46 107 47 108 48 109 110 -
I/O CT pu X 4mA X I/O CT pu X 4mA X
Not connected (not bonded) Not connected (not bonded) I/O CT pu X 4mA X S S X Port 1.15 HDLC: Transmit data output
111 49 112 50 113 51
Ground voltage for digital I/O circuitry Supply voltage for digital I/O circuitry
15/39
STR71xF
Pin n InputLevel TQFP144 Type TQFP64 Pin Name
Input interrupt pu/ pd
Output Capability
Actiive in Stdby
Main function (after reset)
OD
114 115 116 117 118 119 120 121 122
-
A.5 A.6 A.7 A.8 A.9 A.10 A.11 A.12 A.13
O O O O O O O O O
8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA SPI0 Master in/ Slave out data 4mA X X UART3 Transmit data output External Memory Interface: address bus
123 52
P0.0/S0.MISO/ I/O CT pu U3.TX
PP
Alternate function
Port 0.0 Note: Programming AF function selects UART by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. BSPI0: Master out/Slave in data UART3: Receive Data input
124 53
P0.1/S0.MOSI/ I/O CT pu X 4mA X U3.RX
X
Port 0.1 Note: Programming AF function selects UART by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. BSPI0: Serial Clock I2C1: Serial clock
125 54
P0.2/ S0.SCLK/ I1.SCL
I/O CT pu X 4mA X
X
Port 0.2 Note: Programming AF function selects I2C by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. SPI0: Slave Select input active low. I2C1: Serial Data
126 55
P0.3/S0.SS/ I1.SDA
I/O CT pu
4mA X
X
Port 0.3
Note: Programming AF function selects I2C by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register.
127 56 128 57 129 58 130 131 132 133 134 135 136 -
P0.4/S1.MISO VSS18 V18 A.14 A.15 A.16 A.17 A.18 A.19 WE.1
I/O CT pu S S O O O O O O O
4mA X
X
Port 0.4 SPI1: Master in/Slave out data Stabilisation for main voltage regulator. Stabilisation for main voltage regulator. Requires external capacitors of at least 10F + 33nF between V18 and VSS18. See Figure 5.
8mA 8mA 8mA 8mA 8mA 8mA 8mA External Memory Interface: active low MSB write enable output External Memory Interface: address bus
16/39
STR71xF
Pin n InputLevel TQFP144 Type TQFP64 Pin Name
Input interrupt pu/ pd
Output Capability
Actiive in Stdby
Main function (after reset)
OD
PP
Alternate function
137 138
-
WE.0 V33 VSS P0.5/S1.MOSI P0.7/S1.SS
O S S
8mA
External Memory Interface: active low LSB write enable output Supply voltage for digital I/Os Ground voltage for digital I/Os X X X Port 0.5 SPI1: Master out/Slave In data Port 0.6 SPI1: Serial Clock Port 0.7 SPI1: Slave Select input active low Port 0.8 UART0: Receive Data input UART0: Transmit data output.
139 59 140 60 141 61 142 62
I/O CT pu 4mA X P0.6/S1.SCLK I/O CT pu X 4mA X I/O CT pu 4mA X
143 63
P0.8/U0.RX/ U0.TX
I/O CT pd X 4mA T
Note: This pin may be used for single wire UART (half duplex) if programmed as Alternate Function Output. The pin will be tri-stated except when UART transmission is in progress X Port 0.9 Select Boot Con- UART0: Transmit data figuration input output
144 64
P0.9/U0.TX/ BOOT.0
I/O CT pd
4mA X
1. In reset state, these pins configured as Input PU/PD with weak pull-up enabled. They must be configured by software as Alternate Function (see Table 3, "Port Bit Configuration Table," on page 18) to be used by the External Memory Interface. 2. In reset state, these pins configured as Input PU/PD with weak pull-down enabled to output Address 0x0000 0000 using the External Memory Interface. To access memory banks greater than 1Mbyte, they need to be configured by software as Alternate Function (see Table 3, "Port Bit Configuration Table," on page 18).
Figure 5. Recommended External Connection of V18 and V18BKP pins
33 nF 129 128
V18
33 nF 58 57
V18
TQFP144
V18BKP V18
TQFP64
V18BKP V18
54 55 58 59 1F 10 F
25 26 27 28 1F 10 F
17/39
STR71xF
Table 3. Port Bit Configuration Table
Port Configuration Registers (bit) PC0(n) PC1(n) PC2(n) Configuration Output Input 0 0 0 HiZ/AIN TRI AIN 1 0 0 IN TRI TTL 0 1 0 IN TRI CMOS 1 1 0 IPUPD WP CMOS Values 0 0 1 OUT OD N.A. 1 0 1 OUT PP N.A. 0 1 1 AF OD CMOS 1 1 1 AF PP CMOS
Notes: AF: Alternate Function AIN: Analog Input IPUPD: Input Pull Up /Pull Down CMOS: CMOS Input levels HiZ: High impedance IN: Input N.A. not applicable. In Output mode, a read access to the port gets the output latch value).
OD: Open Drain OUT: Output PP: Push-Pull TRI: Tristate TTL: TTL Input levels WP: Weak Push-Pull
18/39
STR71xF
1.4 Memory Mapping
Figure 6. Memory Map
APB Memory Space
0xFFFF FFFF
Addressable Memory Space 4 Gbytes
0xFFFF FFFF 0xFFFF FC00 EIC
0xFFFF F800 0xE000 E000 0xE000 D000 0xE000 C000
EIC WDG RTC TIMER 3 TIMER 2
4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K
4K
7
0xE000 B000
APB2 0xE000 0000
64K
TIMER 1
0xE000 A000
TIMER 0
0xE000 9000 0xE000 8000
CLKOUT ADC reserved IOPORT 2 IOPORT 1 IOPORT 0
6
0xE000 7000
APB1 0xC000 0000
64K
FLASH Memory Space 272 Kbytes + regs
0x4010 DFBF FLASH Registers 0x4010 0000
0xE000 6000 0xE000 5000
5
0xA000 0000 PRCCU
20b
0xE000 4000 0xE000 3000
1K
0x400C 4000
reserved
reserved
0xE000 2000 0xE000 1000
XTI APB BRIDGE 2 REGS
B1F1
8K
0xE000 0000
4
0x8000 0000 Reserved
0x400C 2000 B1F0
8K
0xC001 0000
reserved
4K
0x400C 0000 reserved
0xC000 F000 0xC000 E000 0xC000 D000
reserved HDLC + RAM reserved reserved BSPI 1 BSPI 0 CAN USB + RAM UART 3 UART 2
4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K
3
0x6000 0000 EXTMEM
0x4004 0000
1K
B0F7
64K
0xC000 C000 0xC000 B000
0x4003 0000
2
B0F6
0x4000 0000 FLASH
0xC000 A000 0xC000 9000 0xC000 8000 0x4002 0000 0xC000 7000 0xC000 6000 B0F5
64K
256K+16K+32b
1
64K
0x2000 0000 RAM
0xC000 5000 0xC000 4000
UART 1 UART 0 reserved I2C 1 I2C 0 APB BRIDGE 1 REGS
64K
0x4001 0000
0xC000 3000 B0F4
32K
0xC000 2000
0
0x0000 0000 FLASH/RAM/EMI
0x4000 0x4000 0x4000 0x4000 0x4000
8000 6000 4000 2000 0000
B0F3 B0F2 B0F1 B0F0
8K 8K 8K 8K
0xC000 1000 0xC000 0000
(*) FLASH aliased at 0x0000 0000h by system decoder for booting with valid instruction upon RESET from Block B0 (8 Kbytes)
Reserved
19/39
STR71xF
Figure 7. External Memory Map
Addressable Memory Space 4 Gbytes
0xFFFF FFFF 0xFFFF FC00 EIC
7
0xE000 0000 APB2
6
0xC000 0000 APB1
External Memory Space 64 MBytes
5
0xA000 0000 PRCCU
0x6C00 0x6C00 0x6C00 0x6C00
000C 0008 0004 0000
BCON3 BCON2 BCON1 BCON0
register register register register
4
0x66FF FFFF
0x8000 0000 Reserved
Bank3 CSn.3
16M
3
0x6000 0000 EXTMEM
0x6600 0000 0x64FF FFFF Bank2 CSn.2
16M
0x6400 0000
2
0x4000 0000 FLASH
0x62FF FFFF Bank1 CSn.1
16M
0x6200 0000 0x60FF FFFF
1
CSn.0
0x2000 0000 RAM
Bank0
16M
0x6000 0000
0
0x0000 0000 FLASH/RAM/EMI
Reserved
Drawing not in scale
20/39
STR71xF
2 ELECTRICAL CHARACTERISTICS
2.1 Absolute Maximum Ratings This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take normal precautions to avoid application of any voltage higher than the specified maximum rated voltages. For proper operation, it is recommended that VIN and VO be higher than VSS and lower than V33. Reliability is enhanced if unused inputs are connected to an appropriate logic voltage level (V33 or VSS).
Table 4. Absolute Maximum Ratings.
Value Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.1 -0.3 -0.3 -10 Max +4.0 +4.0 +2.0 +2.0 +4.0 V33 + 0.1 +5.5 +4.0 +10 |200| -55 2000 +150
Symbol V33 V33IO-PLL V18 V18BKP AVDD AVSS VIN IOV ITDV TST ESD
Parameter Voltage on V33 with respect to ground (VSS) Voltage on V33IO-PLL with respect to ground (VSS) Voltage on V18 with respect to ground (VSS) Voltage on V18BKP with respect to ground (VSS) Voltage on AVDD pin with respect to ground (VSS) Voltage on AVSS with respect to ground (VSS) Voltage on true open drain pin (P0.10) with respect to ground (VSS) Voltage on any other pin with respect to ground (VSS) Input current on any pin during overload condition Absolute sum of all input currents during overload condition Storage Temperature ESD Susceptibility (Human Body Model)
Unit V V V V V V V mA mA C V
Note
Stresses exceeding above listed recommended "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN>V33 or VIN21/39
STR71xF
2.2 Operating Conditions
Symbol V33 V33IO-PLL V18BKP AVDD TA TJ Parameter Digital Supply Voltage for I/O circuitry Digital Supply Voltage for I/O circuitry and for PLL reference External Supply Voltage for Backup block (Voltage Regulator off) Analog Supply Voltage for the A/D converter Ambient temperature under bias Junction temperature under bias Value Min 3.0 3.0 1.4 V33 -40 -40 Max 3.6 3.6 1.8 V33 +85 +105 Unit V V V V C C
Note
RAM data retention is guaranteed with V33 not below 2.7 Volt, with the device in low power mode (Stop or Wait for Interrupt).
2.3 LVD Electrical Characteristics V33 = 3.3 10%, TA = -40 / 85 C unless otherwise specified.
Table 5. LVD Electrical Characteristics
Symbol VIT Parameter LVD Threshold Test Conditions Main and LP LVDs Value Min Typ 1.3 Max 1.45 Unit V
22/39
STR71xF
2.4 DC Electrical Characteristics V33 = 3.3V 10%, TA = -40 / 85 C unless otherwise specified.
Table 6. DC Electrical Characteristics
Symbol VIH VIL Parameter Input High Level CMOS Input High Level Input Low Level CMOS Input Low Level Input Hysteresis CMOS Schmitt Trigger Input Hysteresis Schmitt Trigger Output High Level High Current Pins Output High Level Standard Current Pins Output Low Level High Current Pins Output Low Level Standard Current Pins Weak Pull-Up Resistor Weak Pull-Down Resistor P0.15 (WAKEUP) only Push Pull, IOH= 8mA Push Pull, IOH= 4mA Push Pull, IOL= 8mA Push Pull, IOL= 4mA Measured at 0.5V33 Measured at 0.5V33 100 100 Comment With or w/o hysteresis P0.15 (WAKEUP) only With or w/o hysteresis P0.15 (WAKEUP) only 0.4 0.3 V33 - 0.8 V33 - 0.8 0.4 0.4 0.8 0.5 Value Min 0.7V33 1.8 0.3V33 0.7 1.2 Typ Max Unit V V V V V V V V V V k k
VHYS
VOH
VOL
RWPU RWPD
23/39
STR71xF
2.5 AC Electrical Characteristics V33 = 3.3V 10%, TA = 27 C unless otherwise specified.
Table 7. Power Consumption
Symbol IDDRUN IDDWFI IDDLP IDDSTP IDDSB1 IDDSB0 Parameter RUN Mode current WFI Mode current LPWFI Mode current STOP Mode current STANDBY Mode current STANDBY Mode current Conditions MCLK=50 MHz 1 MHz System Clock 32 kHz System Clock Main VReg off, Flash in Power-Down LP VReg and 32kHz Osc on LP VReg, LVD, 32kHz Osc bypassed Value Min Typ See Table 8 3 200 100 15 3 30 10 Max 100 6 Unit mA mA A A A A
Note Note Note
IDDRUN is the power consumption in applications exploiting the full performances of the core (running at the maximum frequency). IDDWFI is the power consumption with PLLs off, VReg and Flash on. This guarantees the minimum interrupt response time. IDDLP is the power consumption with PLLs, Main VReg and Flash off.
Table 8. IDDRUN Typical Data measurements, TA=25C
All Peripheral clocks enabled1) Frequency MCLK=1 MHz PCLK=1 MHz MCLK=8 MHz PCLK=8 MHz MCLK=16 MHz PCLK=8 MHz MCLK=48 MHz PCLK=6 MHz MCLK=64 MHz PCLK=8 MHz
1)
(Reset Configuration) RAM Execution 15 19 23 43 53 Flash Execution 15 20 27 53 N/A
All Peripheral clocks disabled1) RAM Execution 11 15 19 40 48 Flash Execution 11 17 23 50 N/A
Unit
mA
Refer to APBn_CKDIS register description.
24/39
STR71xF
V33 = 3.3V 10%, TA = -40 / 85 C unless otherwise specified.
Table 9. AC Electrical Characteristics
Symbol Parameter Conditions Executing from RAM or external memory fMCLK CPU Frequency Executing from Flash Executing from Flash with RWW Burst Mode disabled (FLASHLP bit =1) fPCLK fCK Peripheral Clock for APB Clock input pin Value Min Typ Max 66 50 45 33 33 16 MHz Unit
2.6 nRSTIN Input Filter Characteristics V33 = 3.3V 10%, TA = -40 / 85 C unless otherwise specified.
Table 10. nRSTIN input Filter Characteristics
Symbol tFR tNFR Parameter nRSTIN Input Filtered Pulse nRSTIN Input Not Filtered Pulse 1.2 Conditions Value Min Typ Max 500 Unit ns s
25/39
STR71xF
2.7 Oscillator Electrical Characteristics V33 = 3.3 10%, TA = -40 / 85 C unless otherwise specified.
Figure 8. Crystal Oscillator and Resonator
RTCXTO
RS CL CL
Table 11. Oscillator Electrical Characteristics
Symbol gm tSTUP Parameter Oscillator Transconductance Oscillator Start-up Time Stable V33 Test Conditions Value Min Typ 8 2.5 Max Unit A/V s
2.8 PLL Electrical Characteristics V33 = 3.3 10%, V33IOPLL = 3.3 10%, TA = -40 / 85 C unless otherwise specified.
Table 12. PLL1 Electrical Characteristics
Symbol fPLLCLK1 Parameter PLL output clock Test Conditions Value Min 1.5 3.0 3.0 Typ Max 165 3.0 8.25 6 Unit MHz MHz MHz MHz
fPLL1x 24
FREF_RANGE = 0 FREF_RANGE = 1
fPLL1
PLL input clock
MX[1:0]='00' or `01' FREF_RANGE = 1 MX[1:0]='10' or `11'
26/39
RTCXTO
RTCXTI
RTCXTI
DEVICE
DEVICE
STR71xF
Symbol
Parameter
Test Conditions FREF_RANGE = 0 MX[1:0]='01' or `11' FREF_RANGE = 0 MX[1:0]='00' or `10' FREF_RANGE = 1 MX[1:0]='01' or `11' FREF_RANGE = 1 MX[1:0]='00' or `10' FREF_RANGE = 0 Stable Input Clock
Value Min Typ 1 2 2 4 Max
Unit MHz MHz MHz MHz
fFREE1
PLL free running frequency
300
s
tLOCK1
PLL lock time
Stable V33IOPLL, V18 FREF_RANGE = 1 Stable Input Clock Stable V33IOPLL, V18 tPLL = 4 MHz, MX[1:0]='11' Global Output division = 32 (Output Clock = 2 MHz) 600 s
tJITTER1 PLL jitter (peak to peak)
0.7
2
ns
Table 13. PLL2 Electrical Characteristics
Symbol fPLLCLK2 fPLL2 Parameter PLL output clock PLL input clock Test Conditions Value Min 1.5 3.0 Typ Max 140 3.0 5 300 Unit MHz MHz MHz s
fPLL x 28
FREF_RANGE = 0 FREF_RANGE = 1 FREF_RANGE = 0 Stable Input Clock Stable V33IOPLL, V18 FREF_RANGE = 1 Stable Input Clock Stable V33IOPLL, V18 tPLL = 4 MHz, MX[1:0]='11' Global Output division = 32 (Output Clock = 2 MHz)
tLOCK2
PLL lock time
600
s
tJITTER2 PLL jitter (peak to peak)
0.7
2
ns
27/39
STR71xF
2.9 Flash Electrical characteristics V33 = 3.3 10%, TA = -40 / 85 C unless otherwise specified.
Table 14. Flash Program/Erase Characteristics 1
Symbol tPW tPDW tPB0 tPB1 tES tES tES tES tRPD tPSL tESL Parameter Word Program Double Word Program Bank 0 Program (256K) Bank 1 Program (16K) Sector Erase (64K) Sector Erase (8K) Bank 0 Erase (256K) Bank 1 Erase (16K) Recovery from Power-Down Program Suspend Latency Erase Suspend Latency Double Word Program Double Word Program Not preprogrammed Preprogrammed Not preprogrammed Preprogrammed Not preprogrammed Preprogrammed Not preprogrammed Preprogrammed Test Conditions Value Typ 40 60 1.6 130 2.3 1.9 0.7 0.6 8.0 6.6 0.9 0.8 2.1 170 4.0 3.3 1.1 1.0 13.7 11.2 1.5 1.3 4.3 300 4.9 4.1 1.36 1.26 17.2 14.0 1.87 1.66 20 10 300 Max(C0) Max(Cmax) Unit s s s ms s s s s s s s
Note
C0: TA = 85 C after 0 cycles Cmax: TA = 85 C after max number of cycles
Table 15. Flash Program/Erase Characteristics 2
Symbol Parameter Endurance Endurance (Bank1 sectors) Data Retention tESR Erase Suspend Rate Conditions Value Min 10 100 20 Typ Max Unit kcycles kcycles Years ms
Min time from Erase Resume to next Erase Suspend
20
28/39
STR71xF
2.10 External Memory Bus Timing V33 = 3.3 10%, TA = -40 / 85 C unless otherwise specified. The tables below use a variable which is derived from the EMI_BCONn registers (described in the STR71x Reference Manual) and represents the special characteristics of the programmed memory cycle.
Symbol tMCLK tC Parameter CPU clock period Memory cycle time wait states Value 1 / fMCLK tMCLK x (1 + [C_LENGTH])
Table 16. EMI Read Operation
Symbol tRCR tRP tRDS tRDH tRAS tRAH tRAT tRRT Parameter Read to CSn Removal Time Read Pulse Time Read Data Setup Time Read Data Hold Time Read Address Setup Time Read Address Hold Time Read Address Turnaround Time RDn Turnaround Time Test Conditions Value Min Typ tMCLK tC 3 3 1.3*tMCLK 3 3 tMCLK Max Unit ns ns ns ns ns ns ns ns
See Figure 9, Figure 10, Figure 11and Figure 12 for related timing diagams.
Table 17. EMI Write Operation
Symbol tWCR tWP tWDS tWDH tWAS tWAH tWAT tWWT Parameter WEn to CSn Removal Time Write Pulse Time Write Data Setup Time Write Data Hold Time Write Address Setup Time Write Address Hold Time Write Address Turnaround Time WEn Turnaround Time Test Conditions Value Min Typ tMCLK tC 3 3 1.3*tMCLK 3 3 tMCLK Max Unit ns ns ns ns ns ns ns ns
See Figure 13, Figure 14, Figure 15 and Figure 16 for related timing diagrams.
29/39
STR71xF
Figure 9. Read Cycle Timing: 16-bit READ on 16-bit Memory
tRAH
A[23:0]
Address tRP
RDn
tRCR
CSn.x
WEn.x
tRDS tRAS tRDH
D[15:0]
(Input)
Data Input
Figure 10. Read Cycle Timing: 32-bit READ on 16-bit Memory
tRAT tRAH tRAH
A[23:0]
Address tRP tRRT
Address tRP
RDn
tRCR
CSn.x
WEn.x
tRAS tRDS tRDH tRDS tRDH
D[15:0]
(Input)
Data Input
Data Input
See Table 16 for read timing data.
30/39
STR71xF
Figure 11. Read Cycle Timing: 16-bit READ on 8-bit Memory
tRAT tRAH tRAH
A[23:0]
Address tRP tRRT
Address tRP
RDn
tRCR
CSn.x
WEn.x
tRAS tRDS tRDH tRDS tRDH
D[7:0]
(Input)
Data Input
Data Input
Figure 12. Read Cycle Timing: 32-bit READ on 8-bit Memory
tRAT tRAH tRAH tRAT tRAH tRAT tRAH
A[23:0]
Address tRP tRRT
Address tRP tRRT
Address tRP tRRT
Address tRP
RDn
tRCR
CSn.x
WEn.x
tRAS tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH
D[7:0]
(Input)
Data Input
Data Input
Data Input
Data Input
See Table 16 for read timing data.
31/39
STR71xF
Figure 13. Write Cycle Timing: 16-bit WRITE on 16-bit Memory
tWAH
A[23:0]
Address
RDn
tWCR
CSn.x
tWAS tWP
WEn.x
tWDS tWDH
D[15:0]
(Output)
Data Output
Figure 14. Write Cycle Timing: 32-bit WRITE on 16-bit Memory
tWAT tWAH tWAH
A[23:0]
address
address
RDn
tWCR
CSn.x
tWP tWWT tWP
WEn.x
tWAS tWDS Data Output tWDH tWDS Data Output tWDH
D[15:0]
(Output)
See Table 17 for write timing data.
32/39
STR71xF
Figure 15. Write Cycle Timing: 16-bit WRITE on 8-bit Memory
tWAT tWAH tWAH
A[23:0]
address
address
RDn
tWCR
CSn.x
tWP tWWT tWP
WEn.x
tWAS tWDS Data Output tWDH tWDS Data Output tWDH
D[7:0]
(Output)
Figure 16. Write Cycle Timing: 32-bit WRITE on 8-bit Memory
tWAT tWAH tWAH tWAT tWAH tWAT tWAH
A[23:0]
address
address
address
address
RDn
tWCR
CSn.x
tWP tWWT tWP tWWT tWP tWWT tWP
WEn.x
tWAS tWDS Data Output tWDH tWDS Data Output tWDH tWDS Data Output tWDH tWDS Data Output tWDH
D[7:0]
(Output)
See Table 17 for write timing data.
33/39
STR71xF
2.11 ADC Electrical Characteristics V33 = 3.3 10%, AVDD = 3.3 10%, TA = -40 / 85 C unless otherwise specified.
Table 18. ADC Electrical Characteristics
Symbol RES VIN fMOD IBW Nch PBR SINAD THD ZIN CIN IADC ISTBY Parameter Resolution Input Voltage Range Modulator Oversampling Frequency Input Bandwidth Number of Input Channels Passband Ripple S/N and Distortion Total Harmonic Distortion Input Impedance Input Capacitance Power Consumption Standby Power Consumption TA = 27 C TA = 27 C 2.5 fMOD = 2 MHz 56 60 1 5 3.0 1 63 74 Test Conditions Sinewave with VIN amplitude 0 Value Min Typ 12 2.5 2.1 fMOD/ 4096 4 0.1 Max Unit bits V MHz kHz n dB dB dB M pF mA A
34/39
STR71xF
3 PACKAGE CHARACTERISTICS
3.1 Package Mechanical Data
Figure 17. 64-Pin Thin Quad Flat Package (10x10)
Dim.
D D1 A1 A A2
mm Min 0.05 1.35 0.17 0.09 12.00 10.00 12.00 10.00 0.50 0 0.45 3.5 0.60 1.00 64 7 0 1.40 0.22 Typ Max 1.60 0.15 0.002 Min
inches Typ Max 0.063 0.006
A A1 A2 b
1.45 0.053 0.055 0.057 0.27 0.007 0.009 0.011 0.20 0.004 0.472 0.394 0.472 0.394 0.020 3.5 0.039 7 0.75 0.018 0.024 0.030 0.008
b
c D D1
E1
E e
E E1 e
c
L L1 N
L1 h L
Number of Pins
Figure 18. 144-Pin Thin Quad Flat Package
Dim.
D D1 D3 A1 108 109 73 72 0.10mm .004 in. b Seating Plane E A A2
mm Min 0.05 1.35 0.17 0.09 1.40 0.22 Typ Max 1.60 0.15 0.002 1.45 0.053 0.27 0.007 0.20 0.004 Min
inches Typ Max 0.063 0.006 0.057 0.011 0.008
A A1 A2 b c D D1 D3 E E1
c
b E3 E1
21.80 22.00 22.20 0.858 0.867 0.874 19.80 20.00 20.20 0.780 0.787 0.795 17.50 0.699 21.80 22.00 22.20 0.858 0.867 0.874 19.80 20.00 20.20 0.780 0.787 0.795 17.50 0.50 0 0.45 3.5 0.60 1.00 144 7 0 0.699 0.020 3.5 0.039 7 0.75 0.018 0.024 0.030
144 1 e
37 36
E3 e K
L1
L h
L L1 N
Number of Pins
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3.2 Thermal Characteristics The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using the following equation: TJ = TA + (PD x JA) Where: - TA is the Ambient Temperature in C, - JA is the Package Junction-to-Ambient Thermal Resistance, in C/W, - PD is the sum of PINT and PI/O (PD = PINT + PI/O), - PINT is the product of IDD and VDD, expressed in Watts. This is the Chip Internal Power. - PI/O represents the Power Dissipation on Input and Output Pins; Most of the time for the applications PI/O < PINT and may be neglected. On the other hand, PI/O may be significant if the device is configured to drive continuously external modules and/ or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: PD = K / (TJ + 273C) Therefore (solving equations 1 and 2): K = PD x (TA + 273C) + JA x PD2 where: - K is a constant for the particular part, which may be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations (1) and (2) iteratively for any value of TA. (3) (2) (1)
Table 19. Thermal characteristics
Symbol Parameter Thermal Resistance Junction-Ambient TQFP 144 - 20 x 20 mm / 0.5 mm pitch Thermal Resistance Junction-Ambient TQFP 64 - 10 x 10 mm / 0.5 mm pitch Value Unit
JA JA
42 45
C/W C/W
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4 ORDER CODES
Table 20. Order Codes FLASH Partnumber Kbytes STR710FZ1T6 128+16 STR710FZ2T6 256+16 STR711FR1T6 STR711FR2T6 STR712FR1T6 STR712FR2T6 128+16 256+16 128+16 256+16 RAM Kbytes 16 64 16 64 16 64 No No Yes
32
EMI Yes Yes
USB Yes Yes Yes
CAN Yes Yes No
I/O Ports 48 48 30
Package TQFP144 20x20 TQFP64 10x10
Temp. Range
-40 to +85C
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5 REVISION HISTORY
Table 21. Revision history Date 17-Mar-2004 05-Apr-2004 08-Apr-2004 15-Apr-2004 Revision 1 2 2.1 2.2 First Release Updated "ELECTRICAL CHARACTERISTICS" on page 21 Corrected STR712F Pinout. Pins 43/42 swapped. PDF hyperlinks corrected. Corrected description of STDBY, V18, VSS18 V18BKP VSSBKP pins 7-Jul-2004 3 Added IDDrun typical data Updated BSPI max. baudrate. Updated "External Memory Bus Timing" on page 29 Corrected Flash sector B1F0/F1 address in Figure 6 on page 19 29-Oct-2004 4 Corrected Table 2, "Device Pin Description," on page 11 TQFP64 TEST pin is 16 instead of 17. Added to TQPFP64 column: pin 7 BOOTEN, pin 17 V33IO-PLL Changed description of JTCK from `External pull-down required' to `External pull-up or pull down required'. Description of Changes
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Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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